1. Field of the Invention
This invention relates to a semiconductor device having a chip-on-chip structure having a semiconductor chip superposed with another semiconductor chip thereon.
2. Description of Related Art
There is a chip-on-chip structure having a pair of semiconductor chips connected together by being opposed at their active surfaces, as one form of a multi-chip semiconductor device having a plurality of semiconductor chips connected with one another to be molded with a resin. In the semiconductor device of such a structure, a pair of semiconductor chips formed with internal connection electrodes in the active surfaces are opposed at their active surfaces and connected together by being aligned on the active surface such that the corresponding ones of internal connection electrodes are connected (internally connected) together.
The internal connection electrodes are formed as bumps projecting from the active surface. The internal connection electrodes, however, have deviations in height. Consequently, when the semiconductor chips at the active surfaces are opposed in parallel with each other, the corresponding internal connection electrodes in each set are not constant in the sum of their heights. For this reason, the internal connection electrodes have a narrow spacing in a set having a greater height sum while the internal connection electrodes have abroad spacing in a set having a smaller height sum. During interconnecting the internal connection electrodes, by crushing under pressure the internal connection electrodes of the set greater in height sum, mutual connection is provided on all the internal connection electrodes including the internal connection electrodes smaller in height sum.
External extension electrodes are provided on one of a pair of semiconductor chips to be connected chip on chip. The external extension electrodes are connected to an external connection member, such as a leadframe. Through the external connection member, the semiconductor device can be connected to another circuit board. In the case internal connection is properly done, a predetermined input/output characteristic is obtained through the external connection member as terminals.
A multiplicity of internal connection electrodes are provided on each semiconductor chip. Unless interconnections are all proper on the corresponding internal connection electrodes, the semiconductor device cannot have a predetermined input/output characteristic hence resulting in the unacceptable product. Confirming an internal connection state is made not only on a completed semiconductor device but also as an intermediate test in the manufacturing process. In the intermediate test, electric characteristics are measured through the external extension electrodes in order to confirm a normality/abnormality of internal connection. Namely, a probe for electrical-characteristic measurement is put on every external extension electrode to examine whether a desired input/output characteristic is available or not. Besides, measurement is made for a conduction at between the external extension electrodes in a particular set.
However, despite electrical connection is made between all the corresponding ones of the internal connection electrodes, there are cases that junction is provided between the internal connection electrodes with a deviation on the active surface from a predetermined relative position. In such a case, junction area is smaller as compared to the case where connection is made in a predetermined relative position between the internal connection electrodes. This reduces the mechanical strength at the junctions, resulting in a fear of a fracture at the junctions even under an application of slight loading. Consequently, the semiconductor device having such junctions between the internal connection electrodes should be determined unacceptable.
However, even in such a case, determination is frequently made as proper in the conventional electrical-method test. This is because a rise in electrical resistance is not to be recognized unless the junction area is decreased between the internal connection electrodes to a considerable extent. It is impossible to determine a size of an junction area in the electrical test.
Meanwhile, even where alignment is accurately done on the active surface, when connection is made between the internal connection electrodes under pressurization or the like, there is a decrease in junction area on the internal connection electrodes in a set having a small height sum. In case there are a number of internal connection electrodes small in junction area, there is a possibility not to provide a junction with sufficient strength at between semiconductor chips through internal connection electrodes. In such a case, junction normality/abnormality cannot be determined in the conventional test method.
Furthermore, poor internal connection, in many cases, results from nonparallel arrangement at the active surfaces of a pair of semiconductor chips to be mutually connected. In such a case, the above frequently causes non-connection at between the internal connection electrodes or unstable connection thereof, in a region the spacing is great between the active surfaces. For such a simple cause of poor connection, the conventional semiconductor device must be examined for a conduction and input/output characteristic by putting a probe on every external extension electrode, thus requiring time and cost upon testing.
It is an object of the present invention to provide a semiconductor device capable of determining whether internal connection has been properly done or not.
Also, another object of the invention is to provide a semiconductor device capable of simply determining a normality/abnormality of internal connection.
A semiconductor device according to one aspect of the invention comprises a first semiconductor chip having, on an active surface, a first internal connection electrode and a first lateral-deviation confirming electrode and a second semiconductor chip having, on an active surface, a second internal connection electrode corresponding to the first internal connection electrode and a second lateral-deviation confirming electrode corresponding to the first lateral-deviation confirming electrode, that are connected opposed at the respective active surfaces. The first lateral-deviation confirming electrode and the second lateral-deviation confirming electrode are arranged in such positions that mutual connection is made when the first internal connection electrode and the second internal connection electrode are connected together in a predetermined relative position in an on-plane direction of the active surface but mutual connection is not made when the first internal connection electrode and the second internal connection electrode deviate by a constant distance or greater in a predetermined lateral-deviation detecting direction on a plane of the active surface within a range to keep mutual connection thereof.
The internal connection electrode and the lateral-deviation confirming electrode may be in a projection (bump) form projecting from the active surface.
According to the invention, even where all the corresponding first and second internal connection electrodes are electrically connected together, when these are connected with a deviation by a predetermined distance or greater in a predetermined lateral-deviation detecting direction from a predetermined relative position on the active plane, connection is not made between the first and second lateral-deviation confirming electrodes. Accordingly, in the case where no electrical conduction is available at between the first and second lateral-deviation confirming electrodes, it is possible to determine that the first and second internal connection electrodes are deviated by a predetermined distance or greater from the predetermined relative position in an on-plane direction of the active surface.
In such a case, the corresponding first and second internal connection electrodes, even if connected to have an electrical conduction, have a decreased junction area and hence a low mechanical strength at the junction. Accordingly, such a semiconductor device can be determined as to whether or not internal connection has been done with a sufficient mechanical strength by examining a presence or absence of an electrical conduction at between the first and second lateral-deviation confirming electrodes.
It is preferred that the first semiconductor chip further comprises a pair of conduction confirming electrodes respectively connected to the first lateral-deviation confirming electrode and the first internal connection electrode, the second semiconductor chip further comprises a wiring connecting between the second lateral-deviation confirming electrode connected to the first lateral-deviation confirming electrode and the second internal connection electrode connected to the first internal connection electrode.
In this case, by examining an electrical conduction at between a pair of conduction confirming electrodes, confirmation is possible on whether or not the first and second lateral-deviation confirming electrodes are electrically connected together.
The size and form of the first and second lateral-deviation confirming electrodes can be desirably defined as long as the foregoing role is to be played. For example, the first and second lateral-deviation confirming electrodes and the first and second internal connection electrodes may be all made in the same size and form. In this case, when the first and second internal connection electrodes are in a predetermined relative position, the first and second lateral-deviation electrodes may be arranged overlapped with a positional deviation from each other. The first and second lateral-deviation confirming electrodes may have different size and form respectively.
One of the first and second lateral-deviation confirming electrodes may be a connection confirming electrode pair including two electrodes. In this case, the other of the first and second lateral-deviation confirming electrodes may be a shorting wiring to electrically short between the connection confirming electrodes in the pair. The two electrodes constituting the connection confirming electrode pair may be placed in an electrically insulated state when not connected by the shorting wiring.
In this case, the connection confirming electrode pair may be provided to be shorted by the shoring wiring when the first and second internal connection electrodes are connected together in a predetermined relative position but not to be shorted when the first and second internal connection electrodes are deviated by a predetermined distance or greater in a predetermined direction on the active surface within a range to keep mutual connection. In also this case, it is similarly possible to know a deviation in the on-plane direction of the active surface by examining a presence or absence of an electrical conduction at between the paired connection confirming electrodes. Thus, determination is possible as to whether the first and second internal connection electrodes are connected with a sufficient junction strength.
It is preferred to provide the first and second lateral-deviation confirming electrodes in a plurality of sets. In this case, there is preferably provided a difference in the predetermined lateral-deviation detecting direction between at least two sets of first and second lateral-deviation confirming electrodes.
According to this structure, in the case where the first and second internal connection electrodes deviate by a predetermined distance or greater from a predetermined relative position in any of a plurality of predetermined lateral-deviation detecting directions on the active surface, contact is not made between the first and second lateral-deviation confirming electrodes in any of the sets. Namely, by examining a presence or absence of an electrical conduction between the first and second lateral-deviation confirming electrodes, it is possible to know a deviation of the first and second internal connection electrodes in a plurality of directions on the active surface.
The first and second lateral-deviation confirming electrodes can be provided four sets not to be connected when the first and second internal connection electrodes deviate by a predetermined distance or greater in any of four lateral-deviation detecting directions given at an angular interval of 90 degrees as viewed from a center of the first and second semiconductor chips. In this case, the first and second internal connection electrodes, even where deviated in any direction on the active surface, can be known of a deviation by a presence or absence of an electrical conduction between the first and second lateral-deviation confirming electrodes.
A semiconductor device according to another aspect of the invention is constructed in such a manner that a first semiconductor chip having a plurality of first internal connection electrodes and a first reference-height electrode that project from the active surface, and a second semiconductor chip having a plurality of second internal connection electrodes corresponding to the first internal connection electrodes and a second reference height electrode corresponding to the first reference height electrode that project from the active surface are connected with active faces opposed at each other. The sum of a height of the first reference height electrode and a height of a second reference height electrode, prior to connection, is smaller than a minimum one of the sums of a height of the internal connection electrode and a height of the corresponding second internal connection electrode, prior to connection.
According to the invention, when the first and second semiconductor chips are approached with the respective active surfaces positioned in parallel with each other, contacted first is the one greatest in height sum of among the corresponding first and second internal connection electrodes. By pressurization for example, the first and second internal connection electrodes greater in height sum are crushed and the active surfaces are approached furthermore. Thereupon, the first and second internal connection electrodes in the sets are connected in the order of greater height sum thereof. After connection at between the first and second internal connection electrodes minimal in height sum, connection (contact) is made between the first and second reference height electrodes.
Namely, in case the first and second reference height electrodes have been connected (contacted), it means that connection has been done on all the sets of first and second internal connection electrodes. Where the sum of the first and second reference height electrodes is sufficient small, when the active surfaces are approached until the first and second reference height electrodes connect (contact) with each other, the minimal ones in height sum of the first and second internal connection electrodes are connected together with a sufficient mechanical strength.
It is practically impossible to measure, on each of the first and second semiconductor chips, each height of the first and second internal connection electrodes and then adjust a height of the reference height electrode to a height meeting the foregoing condition on the basis of the measured value. Accordingly, the first and second reference height electrodes can be provided with a height of a constant value based on the previously-measured height data on a certain number of first and second internal connection electrodes.
Herein, it is assumed that the mean values of previously-measured heights of the first and second internal connection electrodes are a1, a2 and the standard deviations thereof are "sgr"1, "sgr"2. It is also assumed that the weight load in connecting the first and second internal connection electrodes together is in a magnitude to connect all the first and second internal connection electrodes having height deviations of xc2x13"sgr"1, xc2x13"sgr"2. The first and second reference height electrodes can be given a1-3"sgr"1, a2-3"sgr"2, for example.
In this case, the first reference electrode, in many cases, has a height sufficiently lower than the lowest of the first internal connection electrodes. Also, the second reference electrode, in many cases, has a height sufficiently lower than the lowest of the second internal connection electrodes. It is noted herein that the internal connection electrodes are assumably sufficient small in the number. Accordingly, on one semiconductor device, the height sum of the first and second reference height electrodes are, in most cases, given sufficiently smaller than the minimal one in height sum of the corresponding first and second internal connection electrodes. Due to this, in almost all the cases, the connection state between the first and second internal connection electrodes is proper in case the first and second reference height electrodes are in contact with each other.
The first and second internal connection electrodes and the first and second reference height electrodes can be formed by plating, for example. On this occasion, only the first and second internal connection electrodes are grown by respective heights of 3"sgr"1 and 3"sgr"2. Thereafter, the first internal connection electrode and the first reference height electrode are simultaneously grown by a height of a1-3"sgr"1 while the second internal connection electrode and the second reference height electrode are simultaneously grown by a height of a2-3"sgr"2. This provides the first and second internal connection electrodes with respective heights of a1-3"sgr"1, and the first and second reference height electrode with respective heights of a2-3"sgr"2.
Because the first and second reference height electrodes must be made correctly in a predetermined height, fine adjustment may be done by etching or the like after forming by plating.
Incidentally, the electrodes, provided on the first and second semiconductor chips to constitute respective sets, may be structured to serve as both the first and second lateral-deviation confirming electrodes and the first and second reference height electrodes.
A semiconductor device according to still another aspect of the invention comprises a first semiconductor chip having an internal connection electrode and at least one pair of connection confirming electrodes and a second semiconductor chip connected opposed to the first semiconductor chip and having an internal connection electrode corresponding to the internal connection electrode of the first semiconductor chip and a shorting wiring shorting between the connection confirming electrodes in the pair.
The connection confirming electrode pair can include two electrodes in an electrically insulated state when not connected by the shorting wiring. The internal connection electrodes may be formed as projections (bumps). In this case, the internal connection electrode and the connection confirming electrode pair on the first semiconductor chip can be structured as projections in the same height while the internal connection electrode and the shorting wiring on the second semiconductor chip can be structured as projections in the same height.
The internal connection electrode may be provided in plurality. The connection confirming electrode pair is preferably arranged close to any of the internal connection electrodes. Meanwhile, the connection confirming electrode pair is preferably arranged at least three pairs spaced one from another. For example, they can be arranged in a position corresponding to a vicinity of a peripheral edge of the second semiconductor.
According to the invention, in the case where the first and second semiconductor chips at active surfaces (surface forming the internal connection electrode) are in parallel with each other, all the corresponding internal connection electrodes are properly connected, and the connection confirming electrode pair is connected with the shorting wiring to be made into a shorted state. Accordingly, electrical resistance is low in any pair of the connection confirming electrodes.
On the other hand, when the first and second semiconductor chips at active surfaces are not in parallel with each other, connection is possibly not proper on the internal connection electrode in the vicinity of a region in which the spacing between the active surface is the greatest. Also, in case the connection confirming electrode pair is provided in the region in which the active surfaces are distant from each other, such connection confirming electrode pair is not to be sufficiently firmly connected (contacted) with or out of contact with the shorting wiring. Consequently, electrical resistance is high or no conduction is available between the pared connection confirming electrodes. Where there are provided at least three pairs of connection confirming electrodes are arranged spaced from one another, there is a high probability that any of the connection confirming electrode pairs exist in the vicinity of the region in which the spacing between the active surfaces is the greatest.
From the above, it is possible to presume whether the active surfaces are in parallel or not by examining an electrical resistance in each of the connection confirming electrode pairs. Namely, in case the electric resistance is lower than a predetermined value on all the connection confirming electrode pairs, the active surfaces are considered in parallel with each other. On the other hand, in case the electric resistance is higher than a predetermined value or no conduction is available on any of the connection confirming electrode pairs, the active surfaces are considered not in parallel with. In the case where the connection confirming electrode pair is arranged close to any internal connection electrode, there is a high possibility that there is a poor connection also on the internal connection electrode in the visinity of the connection confirming electrode pair high in electrical resistance (no conduction).
Accordingly, such a semiconductor device can be determined whether the internal connection electrode is properly connected or not, by merely measuring an electrical resistance between the pared connection confirming electrodes. Namely, the semiconductor device can be simply determined for normality/abnormality of internal connection. Also, because it can be considered that the spacing between the active surfaces is the greatest in the vicinity of the connection confirming electrode pair in which an electrical resistance is higher than a predetermined value or no conduction is available, it is also possible to simply know an approximate inclination direction of the active surface. It is satisfactory to conduct a detailed test by putting, as required, a probe on every external extension electrodes as before, only on the semiconductor device having an electrical resistance lower than a predetermined value in every connection confirming electrode pair.
The first semiconductor chip may further include external extension electrodes for connection to an external connection member, such as a leadframe. The external extension electrodes, in part, may be electrical-resistance measuring electrode pairs connected one-to-one to the connection confirming electrode pairs. In this case, an electrical resistance can be measured between the paired connection confirming electrodes by putting a probe on the electrical-resistance measuring electrode pair. Because the connection confirming electrode pairs exist between the first and second semiconductor chips, there is a difficulty in directly putting a probe on the connection confirming electrode pair. Contrary to this, the electrical-resistance measuring electrode pairs (external extension electrodes) are arranged in a region where the first and second semiconductor chips are not opposed, a probe can be easily put thereon to measure an electrical resistance. The connection confirming electrode pairs and shorting wirings are small in size and hence low in electrical resistance. Consequently, measuring an electrical resistance is preferably by a four terminal (probe) method in order to obtain correct measurement values.
The semiconductor device may include three or more semiconductor chips. Namely, a plurality of small semiconductor chips may be arranged on one large semiconductor chip. In this case, internal connection can be simply determined for normality/abnormality by a similar technique.
In the case where the second semiconductor chip is rectangular in plan view, the connection confirming electrode pair is preferably arranged, in plan view, in a position on the first semiconductor chip corresponding to a vicinity of a corner of the second semiconductor chip.
Where the active surfaces of the first and second semiconductor chips are not arranged parallel, the spacing between the active surfaces is the greatest at any corner of the second semiconductor chip. In case a connection confirming electrode pair exists in the region where the spacing between the active surfaces is the greatest in this manner, it is possible to locate with probability a poor connection of between the internal connection electrodes.
It is preferred to arrange connection confirming electrode pairs in positions on the first semiconductor chip corresponding to the vicinities of four corners of the second semiconductor chip. In this case, even when the active surface inclines in any direction, the connection confirming electrode pair necessarily exists in a vicinity of a region where the spacing between the active surfaces is the greatest. This makes it possible to locate a poor connection in the internal connection electrode with higher probability.
The internal connection electrodes may be provided, in plan view, both in a vicinity of a peripheral edge and an inner region on the second semiconductor chip. For example, the internal connection electrodes may be arranged in a lattice form extending over the entire active surface of the second semiconductor chip.
The above and other objects, features and effects of the present invention will be made more apparent by the explanation of embodiments which will be described below with reference to the accompanying drawings.